 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ACX302AK 8.80cm (3.5 Type) NTSC/PAL Color LCD Panel Description The ACX302AK is a 8.80cm diagonal active matrix TFT-LCD panel addressed by low temperature polycrystalline silicon transistors with built-in peripheral driving circuitry. This panel provides fullcolor representation for NTSC and PAL systems. In addition, RGB dots are arranged in a delta pattern that provides smooth picture quality without fixed color patterns compared to vertical stripe and mosaic patterns. Features * Number of active dots: 200,000, 8.80cm (3.5 Type) in diagonal * Horizontal resolution: 440 TV lines * Optical transmittance: 8.2% (typ.) * High contrast ratio with normally white mode: 200 (typ.) * Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible) * Low voltage, low power consumption 12V drive: 60mW (typ.) * Smooth pictures with a RGB delta arrangement * Supports NTSC/PAL * Built-in picture quality improvement circuit * Up/down and/or right/left inverse display function * 16:9 screen display function * AR (anti-reflectance) surface treatment provides an easy-to-see display even outdoors * Dirt-resistant surface treatment * Narrow frame * High color reproductivity Element Structure * Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline silicon transistors * Number of pixels Total number of dots : 884 (H) x 230 (V) = 203,320 Number of active dots : 880 (H) x 228 (V) = 200,640 * Panel dimensions Package dimensions : 78.8 (W) x 63.3 (D) x 2.2 (H) (mm) Effective display dimensions : 70.400 (H) x 52.725 (V) (mm) Applications LCD monitors, etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99419A9Z-PS ACX302AK Block Diagram The panel block diagram is shown below. H Level Shifter & Shift Register COM V Shift Register Negative Voltage Generation Circuit Common Voltage V Level Shifter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V Shift Register CS LC 21 22 23 24 COM VSS EN TESTL HVDD HCK2 VVDD GREEN RED RGT VCK HST REF VST -2- Cext/Rext TESTR TEST2 TEST1 VSSG WIDE HCK1 PSIG BLUE DWN ACX302AK Absolute Maximum Ratings (Vss = 0V) * H driver supply voltage HVDD, Cext/Rext * V driver supply voltage VVDD * V driver negative supply voltage VSSG * Common voltage of panel COM * H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE * V driver input pin voltage VST, VCK, EN, DWN, REF * Video signal, uniformity improvement signal input pin voltage GREEN, RED, BLUE, PSIG * Operating temperature Topr * Storage temperature Tstg -1.0 to +17 -1.0 to +15 -3.0 to +1.0 -1.0 to +17 -1.0 to +17 -1.0 to +15 -1.0 to +13 -10 to +60 -30 to +85 V V V V V V V C C Operating Conditions 1. Input/output supply voltage conditions1 Item Symbol HVDD Supply voltage VSSG output voltage setting3 VVDD Cext/Rext2 VSSG Min. 11.4 11.4 HVDD - 2.0 -2.3 Typ. 12.0/13.5 12.0/13.5 12.0/13.5 -1.8 Max. 14.0 14.0 -- -1.5 (Vss = 0V) Unit V V V V 1 The HVDD/VVDD typical voltage setting is noted as 12.0V in these specifications. 2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below. 3 For the VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode as shown in the figure below. The Cext/Rext value differs according to the rising time of the panel supply voltage. ACX302AK HVDD HVDD HVDD Cext/Rext Rext 1F HVDD - Cext/Rext 7 Cext/Rext Cext VSS Use a Zener voltage of 2.7V. (RD2.7UM is recommended.) VSSG Voltage text Time Set a Cext value that satisfies text > 1ms. -3- ACX302AK 2. Input signal voltage conditions Item (Low) H/V driver input voltage REF input voltage Video signal center voltage Video signal input range Uniformity improvement signal 16:9 display top/bottom black signal4 Common voltage of panel (Ta = 25C) (High) Symbol VIL VIH VREF VVC Vsig Vpsig VpsigBK Vcom VVC - 0.4 Min. -0.3 2.6 VIH/2 - 0.3 5.3 1.0 VVC 2.3 Typ. 0.0 3.0 VIH/2 5.5 VVC 4.0 VVC 2.5 VVC 4.0 VVC - 0.3 Max. 0.3 5.5 (Vss = 0V) Unit V V V V V V V V VIH/2 + 0.3 5.7 VVDD - 2.0 (however, 10V or less) VVC 2.7 VVC 4.5 VVC - 0.2 4 Input video and uniformity improvement signals should be symmetrical to VVC. The input conditions for the uniformity improvement signal Vpsig differ for 4:3 display and 16:9 display. 1) During 4:3 display, input the voltage amplitude symmetrical to VVC as shown in Fig. 1. 2) During 16:9 display, input the same signal amplitude as in 1) above during the effective display portion, and input the black signal level VpsigBK during the top/bottom black input portion as shown in Fig. 2. During 4:3 display PSIG VVC Vpsig Fig. 1 During 16:9 display PSIG VVC Vpsig VpsigBK VVC 4.0V VVC 2.5V Top/bottom black display portion (letterbox portion) Effective display portion Fig. 2 -4- ACX302AK Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol TESTL COM VST VCK EN DWN VVDD VSS HVDD VSSG TEST2 WIDE Description Panel test output; no connection Common voltage input of panel Start pulse input for V shift register drive Clock input for V shift register drive Gate selection pulse enable input V shift register drive direction signal input Power supply input for V driver H and V driver GND Power supply input for H driver Negative power supply setting for V driver Test; no connection Pulse input for 16:9 mode Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 Symbol HST REF TEST1 Cext/ Rext HCK2 HCK1 PSIG Description Start pulse input for H shift register drive Level shifter circuit REF voltage input Panel test output; no connection Time constant power supply input for H shift register drive Clock input for H shift register drive Clock input for H shift register drive Uniformity improvement signal input GREEN Video signal (G) input to panel RED BLUE RGT TESTR Video signal (R) input to panel Video signal (B) input to panel H shift register drive direction signal input Panel test output; no connection -5- ACX302AK Input Equivalent Circuits To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal input pins. All pins are connected to Vss with a high resistance of 1M (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.) (1) RED, GREEN, BLUE, PSIG HVDD Input 1M Signal line (2) HCK1, HCK2 HVDD HVDD HCK1 1M HCK2 1M H level shifter and shift register circuit (3) HST, WIDE, REF HVDD HVDD 350 Input 1M REF 1M 350 Level conversion circuit (4) RGT, REF HVDD HVDD 2k Input 1M REF 1M 2k Level conversion circuit (5) VST, VCK, EN, REF VVDD VVDD 800 Input 1M REF 1M 800 Level conversion circuit -6- ACX302AK (6) DWN, REF VVDD VVDD 2k Input 1M REF 1M 2k Level conversion circuit (7) VSSG HVDD Negative voltage generation circuit VSSG (8) COM Input 1M LC (9) Cext/Rext HVDD Cext/Rext 1M H driver (10) TEST1/TEST2 HVDD 350 TEST1 1M 350 TEST2 1M (11) TESTL, TESTR TESTL TESTR -7- ACX302AK Clock Timing Conditions Item HST rise time HST HST fall time HST data setup time HST data hold time HCKn rise time HCK HCKn fall time HCK15 fall to HCK2 rise time HCK15 rise to HCK2 fall time VST rise time VST VST fall time VST data setup time VST data hold time VCK VCK rise time VCK fall time EN rise time EN EN fall time EN rise to VCK rise/fall time EN pulse width WIDE rise time WIDE fall time WIDE (H) rise to VCK rise/fall time WIDE WIDE (H) pulse width WIDE (V) pulse width WIDE (V) fall to EN rise time EN fall to WIDE (V) fall time 5 HCKn means HCK1 and HCK2. (fHCKn = 3.0MHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVckn tfVckn trEn tfEn tdEn twEn trWide tfWide tdhWide twhWide twvWide tov1Wide tov2Wide (VIH = 3.0V, HVDD = VVDD = 12V, Ta = 25C) Min. -- -- 137 -30 -- -- -15 -15 -- -- 30 -34 -- -- -- -- 2400 5400 -- -- 0.9 2.8 1928 25 25 Typ. -- -- 167 0 -- -- 0 0 -- -- 32 -32 -- -- -- -- 2500 5500 -- -- 1.1 3.0 1933 32 32 Max. 30 30 197 30 30 30 15 15 100 100 34 -30 100 100 100 100 2600 5600 100 100 1.3 3.3 1938 -- -- s ns s ns Unit -8- ACX302AK Horizontal Standard Timing 5.0s HST HCK1 HCK2 1.3s FRP VCK 2.5s EN 3s WIDE6 1.1s 1.9s 6 WIDE represents every 1H pulse indicated on the horizontal timing. -9- ACX302AK HST 10% trHst Waveform 90% 90% 10% tfHst Conditions * HCKn5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst 7 HST HST data setup time tdHst HST 50% 50% HCK1 50% 50% HST data hold time thHst tdHst thHst * HCKn5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns HCKn5 rise time trHckn 5 HCKn 90% 10% 90% 10% HCKn5 fall time HCK HCK1 fall to HCK2 rise time tfHckn 7 to1Hck HCK1 50% trHckn tfHckn * HCKn5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 167ns thHst = 0ns 50% 50% 50% * tdHst = 167ns thHst = 0ns HCK1 rise to HCK2 fall time HCK2 to2Hck to2Hck to1Hck WIDE rise time trWide WIDE 10% 90% 90% 10% tfWide WIDE fall time 6 WIDE WIDE fall to VCK rise/fall time tfWide trWide tdhWide VCK 50% 50% twWide tdWide 50% WIDE WIDE pulse width twhWide 7 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means -. The black dot at an arrow ( ) indicates the start of measurement. - 10 - ACX302AK Vertical Standard Timing NTSC 4:3 (in case of EVEN field) VST VCK FRP HST EN WIDE NTSC WIDE (in case of EVEN field) VST VCK FRP HST EN WIDE 8 8 WIDE represents 1F period indicated on the vertical timing. - 11 - ACX302AK VST 10% 10% tfVst Waveform 90% 90% Conditions * VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tfVst 7 trVst VST VST data setup time tdVst VST 50% 50% 50% 50% VCK VST data hold time thVst tdVst thVst * VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns VCK rise time VCK VCK fall time trVck VCK 90% 10% 90% 10% tfVck trVck tfVck * VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32s thVst = -32s * VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns EN rise time EN fall time trEn EN 90% 10% 10% 90% tfEn 7 VCK tfEn trEn EN EN fall to VCK rise/fall time tdEn 50% EN 50% tdEn twEn 50% EN pulse width twEn WIDE rise time trWide WIDE 10% 90% 90% 10% tfWide WIDE fall time tfWide trWide 8 WIDE WIDE pulse width twvWide WIDE 50% twWide 50% 7 WIDE fall to EN fall time tov1Wide WIDE trWide 50% EN 50% 50% to1Wide EN rise to WIDE fall time tov2Wide to2Wide - 12 - ACX302AK Electrical Characteristics (Ta = 25C, HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V) 1. Horizontal drivers Item HCKn input pin capacitance HST input pin capacitance Video signal input pin capacitance Psig input pin capacitance (4:3 display) Psig input pin capacitance (16:9 display) Input pin current HCK1 HCK2 HST RGT REF Current consumption (Ta = 25C) (Ta = 60C) Symbol CHckn CHst Csig Cpsig Cpsig I Hck1 I Hck2 I Hst I RGT I REF I H25 I H60 Min. -- -- -- -- -- -900 -900 -300 -150 -1200 -- -- Typ. 80 30 270 16 45 -300 -300 -100 -50 -300 4.0 -- Max. 95 45 310 20 50 -- -- -- -- -- 4.75 6.00 Unit pF pF pF nF nF A A A A A mA mA HCK1: actual driving HCK2: actual driving HST = GND RGT = GND REF = VIH/2 Conditions HCKn: HCK1, HCK2 (3.0MHz) 2. Vertical drivers Item VCK input pin capacitance VST input pin capacitance Input pin current VCK VST EN DWN WIDE Current consumption (Ta = 25C) (Ta = 60C) Symbol CVck CVst I Vck I Vst I En I DWN I WIDE I V25 I V60 Min. -- -- -150 -150 -150 -150 -150 -- -- Typ. 10 10 -50 -50 -50 -50 -50 1.0 -- Max. 15 15 -- -- -- -- -- 1.5 2.0 Unit pF pF A A A A A mA mA VCK = GND VST = GND EN = GND DWN = GND WIDE = GND Conditions 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) (Ta = 25C) (Ta = 60C) Symbol PWR25 PWR60 Min. -- -- Typ. 60 -- Max. 75 96 Unit mW mW 4. Pin input resistance Item Pin - VSS input resistance Symbol Rin Min. 0.5 - 13 - Typ. 1 Max. -- Unit M ACX302AK Electro-optical Characteristics Item Contrast ratio Optical transmittance X R Y X G Y X B Y 25C V90 V-T characteristics 60C 25C V50 60C 25C V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time 60C R-G B-G 0C 25C 0C 25C 60C 1 min. CR 10 = 0 25C 25C 60C Symbol CR25 CR60 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT1 T B L R Rf CTK 7 8 6 5 4 3 Measurement method 1 2 Min. 100 100 7.7 0.595 0.310 0.245 0.580 0.120 0.090 1.30 1.30 1.70 1.70 2.20 2.20 -0.050 0.000 -- -- -- -- -- -- 35 50 45 45 -- -- (Ta = 25C, NTSC mode) Typ. 200 200 8.2 0.625 0.340 0.275 0.610 0.150 0.120 1.50 1.50 1.90 1.90 2.40 2.40 -0.080 0.030 40 15 140 50 -60 -- 45 60 55 55 0.9 Max. -- -- -- 0.655 0.370 0.305 0.640 0.180 0.150 1.70 1.70 2.10 2.10 2.60 2.60 -0.110 0.050 55 25 180 75 -30 10 dB s Degree () % % ms V V CIE standards Unit -- % Chromaticity Viewing angle range 9 -- Surface reflection ratio Cross talk 10 11 1.5 1.5 - 14 - ACX302AK Surface A Backlight Luminance Meter 3.5mm LCD panel Measurement Equipment Measurement system II Optical fiber Light receptor lens Surface A Light Detector Measurement Equipment Drive Circuit LCD panel Light Source Measurement system III Light Source Optical fiber Spectroscope Surface A Surface A: See the Package Outline. 1. Contrast Ratio Contrast ratio (CR) is given by the following formula. CR = L (White)/L (Black) L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.0V. Both luminosities are measured by System I. - 15 - ACX302AK 2. Optical Transmittance Optical transmittance (T) is given by the following formula. T = L (White)/Luminance of Backlight x 100 [%] L (White) is the same expression as defined in the "Contrast Ratio" section. Optical transmittance is measured by System I. 3. Chromaticity Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses x and y of the CIE standards as the chromaticity here. Signal amplitudes (VAC) supplied to each input R input R Raster G B W 0.5 4.0 4.0 0.0 G input 4.0 0.5 4.0 0.0 B input 4.0 4.0 0.5 0.0 (Unit: V) 4. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panel, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. Transmittance [%] 90 50 10 V90 V50 V10 VAC - Signal amplitude [V] 5. Half Tone Color Reproduction Range The half tone color reproduction range of LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G and B raster mode which correspond to 50% of transmittance, V50R, V50G and V50B, respectively. V50RG and V50BG, that is to say the differences between V50R and V50G and between V50B and V50G, are given by the following formulas respectively. V50RG = V50R - V50G V50BG = V50B - V50G - 16 - 100 V50RG V50BG Transmittance [%] 50 R raster G raster B raster 0 V50R V50B V50G VAC - Signal amplitude [V] ACX302AK 6. Response Time Response times ton and toff are measured by System II by applying the input signal voltages in the figure to the right to each input pin. These times are defined by the following formulas. ton = t1 - tON toff = t2 - tOFF t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the figure to the right. Input signal voltage (Waveform applied to measured pixels) 4.0V 5.5V 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of the panel output signal for gray raster* mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20 log {AC component/DC component} R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 V50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve. 8. Image Retention Time Image retention time is given by the following procedures. Apply the monoscope pattern to the LCD panel for 1 minute and then change to a gray scale signal (Vsig = 5.5 VAC (V); VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time for the residual image to disappear. Monoscope pattern input conditions Vsig = 5.5 4.0 or 5.5 2.0 [V] (shown in the figure to the right) Vcom = 5.20V Black level 4.0V 2.0V 5.5V 2.0V 4.0V White level 0V Vsig waveform - 17 - ACX302AK 9. Definition of Viewing Angle Range Viewing angle range is measured by System I. The contrast ratio (CR) is measured at the angles defined in the figure to the right and the range where CR 10 is taken as the viewing angle range. Measure with surface A facing upwards. Surface A: See the Package Outline. Normal ( = 0) B T L Left R Top Bottom Right Surface A 10. Surface Reflection Ratio Surface reflection ratio (Rf) is given by the following formula. Rf = Reflected optical luminance of the panel surface A/Reflected optical luminance of Al (wafer) x 100 [%] The incident and reflected angles of light are both 0. Both luminosities are measured by System III. Surface A: See the Package Outline. 11. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around the black window (Vsig = 4.0V/1V). Wi' - Wi Wi x 100 [%] W1 W1' W2 W2' W4 W4' Cross talk value CTK = W3 W3' 12. Measurement Backlight Specifications Optical characteristics Item Average luminance of effective illuminating surface Color temperature (reference value) Chromaticity coordinates Standard 2,700 300 8,800 x: 0.285 0.01 y: 0.303 0.01 - 18 - Unit cd/m2 K Remarks Ta = 25 2C, at dimmer = max. Ta = 25 2C, at dimmer = max. ACX302AK Description of Operation 1. Color Coding The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R 228 G B R G B R G R G B R G B R G B R G B R G R G B R G B R 2 G B Active area B R R G B R G B R 1 R G B R G B R G B R G B R G B R G B R G B R G B R G B R B R G B R G B R G B 2 880 884 - 19 - 1 230 ACX302AK 2. Description of LCD Panel Operations * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to each of 228 line electrodes sequentially one line electrode at a time in a single horizontal scanning period. * The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display and 16:9 mode pulse elimination display are possible by using the enable pin and simultaneously controlling VCK. * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry, applies selected pulses to each of 880 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. * The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top for DWN pin at low level (0V). (These scanning directions are from a front view.) * The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 228 x 880 pixels to display a picture in a single vertical scanning period. * Pixel dots are arranged in a delta arrangement, where sets of RGB pixels are positioned shifted by 1.5 dots against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal line against the horizontal sync signal to apply a video signal to each pixel properly. * The video signal should be input with the polarity-inverted every horizontal cycle. * The relationships between the vertical shift register start pulse VST and the vertical display period, and between the horizontal shift register start pulse HST and the horizontal display period are shown below for top to bottom and left to right scan. (1) Vertical display period (DWN: high level) VD VST VCK 1 2 227 228 Vertical display period 228H (14.5ms) (2) Vertical display period (DWN: low level) VD VST VCK 1 2 227 228 Vertical display period 228H (14.5ms) (3) Horizontal display period (RGT: high level) BLK HST 294 HCK1 1 2 3 293 295 Horizontal display period (48.9s) HCK2 - 20 - ACX302AK 3. RGB Simultaneous Sampling The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching by an external signal delay circuit is needed before applying the video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuits. These two block diagrams are as follows. The ACX302AK has a right/left inversion function. The following phase relationship diagram indicates the phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be inverted for the B and G signals. (1) Sample-and-hold (right scan) B S/H S/H AC Amp 22 BLUE R S/H S/H AC Amp 21 RED CKR G CKG S/H CKG AC Amp 20 GREEN HCKn CKB CKR CKG (2) Delay element (right scan) B Delay Delay AC Amp 22 BLUE R Delay AC Amp 21 RED G AC Amp 20 GREEN - 21 - ACX302AK ACX302AK CKB CKG ACX302AK System Configuration +12.0V +3.0V +12.0V PSIG Y/color difference R/G/B RED GREEN BLUE COM/CS HST HCK1 CXA3268AR Serial data HCK2 VST VCK DWN EN RGT REF WIDE VSSG 1F LCD Panel ACX302AK Cext/Rext 10k Cext See page 3 for the value setting. Use a Zener voltage of 2.7V. (RD2.7UM is recommended.) Control Circuit - 22 - ACX302AK Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install grounded conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stains on the surface. c) Use ionized air to blow dust off the panel. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at high temperatures or high humidity, as this may result in panel damage. - 23 - Package Outline Unit: mm 78.8 (39.9) 74.3(Window) (3.35) (36.55) 720.5 (Polarizer) 38.9 (2.75) 73.1(Window) 36.55 2.35 1FPC 2 Reinforcing board 3 Polarizer 4 Shield case(Front) 5Shield case(Rear) 6 Double coated adhesive tape 1.75 (37.15) 37.15 730.5 (Polarizer) 2.2 2.73 3.33 70.4(Active area) 5 4 6 3 31.08 28.35 28.35 (Polarizer) 32 55.4 0.5 56.7(Window) 63.3 (Polarizer) Center (reference) Center (Reference) 52.725(Active area) (32.22) (28.3) (28.35) 2 0.3 0.05 12.5 0.05 30 0.5 (3.87) Pin24 Pin1 Thickness of the connector 12.8 0.5 Note1. Tolerance with no indicate(0.2) 2. SONY logotype 3. Label is stuck hear Mass: Approximately 25g 0.35 (0.5) 0.03 P : 0.50.02x23=11.50.03 0.5 ACX302AK Electrode Enlarged(Back) (4.47) - 24 - Note 2 1 54.4 0.5 55.5(Window) 3 6 Front view Rear view Note 3 |
Price & Availability of ACX302
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |